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cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 18-mbit ddr-ii+ sram 2-word burst architecture (2.0 cycle read latency) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-06621 rev. *c revised june 21, 2007 features 18 mbit density (2m x 8, 2m x 9, 1m x 18, 512k x 36) 300 mhz to 375 mhz clock for high bandwidth 2-word burst for reducing address bus frequency double data rate (ddr) interfaces (data transferred at 750 mhz) @ 375 mhz read latency of 2.0 clock cycles two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only echo clocks (cq and cq ) simplify data capture in high-speed systems data valid pin (qvld) to indicate valid data on the output synchronous internally self-timed writes core v dd = 1.8v 0.1v; io v ddq = 1.4v to v dd [1] hstl inputs and variable drive hstl output buffers available in 165-ball fbga package (13 x 15 x 1.4 mm) offered in both pb-free and non pb-free packages jtag 1149.1-compatible test access port delay lock loop (dll) for accurate data placement configurations with read cycle latency of 2.0 cycles: cy7c1146v18 ? 2m x 8 cy7c1157v18 ? 2m x 9 cy7c1148v18 ? 1m x 18 cy7c1150v18 ? 512k x 36 functional description the cy7c1146v18, cy7c1157v18, cy7c1148v18, and cy7c1150v18 are 1.8v synchronous pipelined srams equipped with ddr-ii+ architectu re. the ddr-ii+ consists of an sram core with advanced synchronous peripheral circuitry. addresses for read and write are latched on alternate rising edges of the input (k) clock. writ e data is registered on the rising edges of both k and k . read data is driven on the rising edges of k and k . each address location is associated with two 8-bit words (cy7c1146v18) or 9-bit words (cy7c1157v18) or 18-bit words (cy7c1148v18) or 36-bit words (cy7c1150v18) that burst sequentially into or out of the device. asynchronous inputs include output impedance matching input (zq). synchronous data outputs (q, sharing the same physical pins as the data inputs d) ar e tightly matched to the two output echo clocks cq/cq , eliminating the need for separately capturing data from each individual ddr sram in the system design. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the k or k input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. selection guide 375 mhz 333 mhz 300 mhz unit maximum operating frequency 375 333 300 mhz maximum operating current 1020 920 850 ma note 1. the qdr consortium specification for v ddq is 1.5v + 0.1v. the cypress qdr devices exceed the qdr consor tium specification and are capable of supporting v ddq = 1.4v to v dd . [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 2 of 27 logic block diagram (cy7c1146v18) logic block diagram (cy7c1157v18) clk a (19:0) gen. k k control logic address register read add. decode read data reg. r/w dq [7:0] output logic reg. reg. reg. 8 8 16 8 nws [1:0] v ref write add. decode 8 8 ld control 20 1m x 8 array 1m x 8 array write reg write reg cq cq r/w doff qvld 8 clk a (19:0) gen. k k control logic address register read add. decode read data reg. r/w dq [8:0] output logic reg. reg. reg. 9 9 18 9 bws [0] v ref write add. decode 9 9 ld control 20 1m x 9 array 1m x 9 array write reg write reg cq cq r/w doff qvld 9 [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 3 of 27 logic block diagram (cy7c1148v18) logic block diagram (cy7c1150v18) clk a (18:0) gen. k k control logic address register read add. decode read data reg. r/w dq [17:0] output logic reg. reg. reg. 18 18 36 18 bws [1:0] v ref write add. decode 18 18 ld control 19 512k x 18 array 512k x 18 array write reg write reg cq cq r/w doff qvld 18 clk a (17:0) gen. k k control logic address register read add. decode read data reg. r/w dq [35:0] output logic reg. reg. reg. 36 36 72 36 bws [3:0] v ref write add. decode 36 36 ld control 18 256k x 36 array 256k x 36 array write reg write reg cq cq r/w doff qvld 36 [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 4 of 27 pin configurations cy7c1146v18 (2m x 8) 165-ball fbga (13 x 15 x 1.4 mm) pinout 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a nws 1 k r/w nc/144m nc nc nc nc nc tdo nc nc nc nc nc nc tck nc nc a nc/288m k nws 0 v ss aaa nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd dq4 nc v ddq nc nc nc nc dq7 a v ddq v ss v ddq v dd v dd dq5 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a nc v ss a a a nc v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss qvld nc dq6 nc nc nc v dd a 891011 nc a nc/36m ld cq a nc nc dq3 v ss nc nc nc nc v ss nc dq2 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq nc v ddq nc dq1 nc v ddq v ddq nc v ss nc nc nc tdi tms v ss a nc a nc nc nc zq nc dq0 nc nc nc nc a cy7c1157v18 (2m x 9) 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a nc k r/w nc/144m nc nc nc nc nc tdo nc nc nc nc nc nc tck nc nc a nc/288m k bws 0 v ss aaa nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd dq4 nc v ddq nc nc nc nc dq7 a v ddq v ss v ddq v dd v dd dq5 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a nc v ss a a a nc v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss qvld nc dq6 nc nc nc v dd a 891011 dq8 a nc/36m ld cq a nc nc dq3 v ss nc nc nc nc v ss nc dq2 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq nc v ddq nc dq1 nc v ddq v ddq nc v ss nc nc nc tdi tms v ss a nc a nc nc nc zq nc dq0 nc nc nc nc a [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 5 of 27 pin configurations (continued) cy7c1148v18 (1m x 18) 165-ball fbga (13 x 15 x 1.4 mm) pinout 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a bws 1 k r/w nc/144m dq9 nc nc nc nc tdo nc nc nc nc nc nc tck nc nc a nc/288m k bws 0 v ss anca dq10 v ss v ss v ss v ss v dd a v ss v ss v ss v dd dq11 nc v ddq nc dq14 nc dq16 dq17 a v ddq v ss v ddq v dd v dd dq13 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a nc v ss a a a nc v ss nc v ss dq12 nc v ref v ss v dd v ss v ss a v ss qvld nc dq15 nc nc nc v dd a 891011 dq0 a nc/36m ld cq a nc nc dq8 v ss nc dq7 nc nc v ss nc dq6 nc nc nc v ref nc dq3 v ddq nc v ddq nc dq5 v ddq v ddq v ddq nc v ddq nc dq4 nc v ddq v ddq nc v ss nc nc nc tdi tms v ss a nc a nc nc nc zq nc dq2 nc dq1 nc nc a cy7c1150v18 (512k x 36) 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/144m nc/36m bws 2 k r/w bws 1 dq27 dq18 nc nc nc tdo nc nc dq31 nc nc nc tck nc dq28 a bws 3 k bws 0 v ss anca dq19 v ss v ss v ss v ss v dd a v ss v ss v ss v dd dq20 dq21 v ddq dq32 dq23 dq34 dq25 dq26 a v ddq v ss v ddq v dd v dd dq22 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a nc v ss a a a dq29 v ss nc v ss dq30 nc v ref v ss v dd v ss v ss a v ss qvld nc dq33 nc dq35 dq24 v dd a 891011 dq0 a nc/72m ld cq a nc nc dq8 v ss nc dq17 dq7 nc v ss nc dq6 dq14 nc nc v ref nc dq3 v ddq nc v ddq nc dq5 v ddq v ddq v ddq dq4 v ddq nc dq13 nc v ddq v ddq nc v ss nc dq1 nc tdi tms v ss a nc a dq16 dq15 nc zq dq12 dq2 dq10 dq11 dq9 nc a [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 6 of 27 pin definitions pin name io pin description dq [x:0] input output- synchronous data input output signals . inputs are sampled on the rising edge of k and k clocks when write operations are valid. these pins drive out the requested data when a read operation is active. valid data is driven out on the rising edge of both the k and k clocks when read operations are active. when read access is deselected, q [x:0] are automatically tri-stated. cy7c1146v18 ? dq [7:0] cy7c1157v18 ? dq [8:0] cy7c1148v18 ? dq [17:0] cy7c1150v18 ? dq [35:0] ld input- synchronous synchronous load . this input is brought low when a bus cycle sequence is to be defined. this definition includes address and read/w rite direction. all transactions operate on a burst of two data. ld must meet the setup and hold times around edge of k. nws 0 , nws 1 , input- synchronous nibble write select 0, 1 ? active low .( cy7c1146v18 only ) sampled on the rising edge of the k and k clocks when the write operation is active. it is used to select the nibble that is written into the device nws 0 controls d [3:0] and nws 1 controls d [7:4] . all the nibble write selects are sampled on the same edge as the data. deselecting a nibble write select causes the corresponding nibble of data to be ignored and not written into the device. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2, and 3 ? active low . sampled on the rising edge of the k and k clocks when the write operation is active. it is used to se lect the byte that is written into the device when the current portion of the writ e operation is active. bytes not written remain unaltered. cy7c1157v18 ? bws 0 controls d [8:0] cy7c1148v18 ? bws 0 controls d [8:0] , and bws 1 controls d [17:9]. cy7c1148v18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] , and bws 3 controls d [35:27] . all the byte write selects are sampled on the same edge as the data. deselecting a byte write select causes the corresponding byte of data to be ignored and not written into the device. a input- synchronous address inputs . sampled on the rising edge of the k clock during active read and write operations. these address inputs are multiplexed for both read and write operations. internally, the device is organized as 2m x 8 (two arrays each of1m x 8) for cy7c1146v18, 2m x 9 (two arrays each of 1m x 9) for cy7c1157v18, 1m x 18 (two arrays each of 512k x 18) for cy7c1148v18, and 512k x 36 (two arrays each of 256k x 18) for cy7c1150v18. all the address inputs are ignored when the appropriate port is deselected. r/w input- synchronous synchronous read/write input . when ld is low, this input designates the access type (read when r/w is high, write when r/w is low) for loaded address. r/w must meet the setup and hold times around edge of k. qvld valid output indicator valid output indicator . the q valid indicates valid output data. qvld is edge aligned with cq and cq . k input- clock positive input clock input . the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input- clock negative input clock input . k is used to capture synchronous inputs being presented to the device and to drive out data through q [x:0] when in single clock mode. cq clock output synchronous echo clock outputs . this is a free running clock and is synchronized to the input clock (k) of the ddr-ii+. the timings for the echo clocks are shown in the ?switching char acteristics? on page 22 . cq clock output synchronous echo clock outputs . this is a free running clock and is synchronized to the input clock (k ) of the ddr-ii+. the ti mings for the echo clocks are shown in the ?switching char acteristics? on page 22 . zq input output impedance matching input . this input is used to tune the device outputs to the system data bus impedance. cq, cq, and q [x:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternat ively, connect this pin directly to v ddq , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 7 of 27 doff input dll turn off ? active low . connecting this pin to ground turns off the dll inside the device. the timings in the dll turned off operation are differen t from those listed in this data sheet. for normal operation, connect this pin to a pull up through a 10 k ? or less pull up resistor. the device behaves in ddr-i mode when the dll is turned off. in this mode, operate the device at a frequency of up to 167 mhz with ddr-i timing. tdo output tdo for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc n/a not connected to the die . tie to any voltage level. nc/36m n/a not connected to the die . tie to any voltage level. nc/72m n/a not connected to the die . tie to any voltage level. nc/144m n/a not connected to the die . tie to any voltage level. nc/288m n/a not connected to the die . tie to any voltage level. v ref input- reference reference voltage input . static input used to set the refer ence level for hstl inputs, outputs, and ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) pin name io pin description [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 8 of 27 functional overview the cy7c1146v18, cy7c1157v18, cy7c1148v18, and cy7c1150v18 are synchronous pipelined burst srams equipped with a ddr interface. accesses are initiated on the rising edge of the positive input clock (k). all synchronous input and output timings refer to the rising edge of the input clocks (k/k ). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the rising edge of the input clocks (k/k ). all synchronous data outputs (q [x:0] ) pass through output registers controlled by the rising edge of the input clocks (k/k ) as well. all synchronous control (r/w , ld , bws [0:x] ) inputs pass through input registers controlled by the ri sing edge of the input clock (k). cy7c1148v18 is described in the following sections. the same basic descriptions apply to cy7c1146v18, cy7c1157v18, and cy7c1150v18. read operations the cy7c1148v18 is organized internally as a single array of 1m x 18. accesses are complete d in a burst of two sequential 18-bit data words. read operations are initiated by asserting r/w high and ld low at the rising edge of the positive input clock (k). the address presented to address inputs are stored in the read address register. following the next two k clock rise the corresponding 18-bit word of data from this address location is driven onto the q [17:0] using k as the output timing reference. on the subsequent rising edge of k the next 18-bit data word from the address location generated by the burst counter is driven onto the q [17:0] . the requested data is valid 0.45 ns from the rising edge of the input clock (k/k ). to maintain the internal logic, each read access must be enabled to complete. initiate read accesses on every rising edge of the positive input clock (k). when read access is deselected, the cy7c1148v18 first completes the pending read transactions. synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the positive input clock (k). this enables a seamless transition between device s without the insertion of wait states in a depth expanded memory. write operations write operations are init iated by asserting r/w low and ld low at the rising edge of the positive input clock (k). the address presented to address inputs is stored in the write address register. on the following k clock rise the data presented to d [17:0] is latched and stored into the 18-bit write data register provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ) the information presented to d [17:0] is also stored into the write data register provided bws [1:0] are both asserted active. the 36 bits of data is then written into the memory array at the specified location. initiate write accesses on every rising edge of the positive input clock (k). this pipelines the data flow such that 18 bits of data transfers into the device on ever y rising edge of the input clocks (k and k ). when write access is deselected, the device ignores all inputs after the pending write operations are completed. byte write operations byte write operations are s upported by the cy7c1148v18. a write operation is initiated as described in the write operations . the bytes that are writte n are determined by bws 0 and bws 1 which are sampled with each set of 18-bit data word. asserting the appropriate byte write select input when the data portion of a write enables the data presente d to be latched and written into the device. deasserting the byte write select input when the data portion of a write enables th e data stored in the device for that byte to remain unaltered. use this feat ure to simplify read/modify/write operations to a byte write operation. double data rate operation the cy7c1148v18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. the cy7c1148v18 requires two no operation (nop) cycle when transitioning from a read to a write cycle. at higher frequenc ies, some applications may require a third nop cycle to avoid contention. if a read occurs after a write cycl e, address and data for the write are stored in registers. the wr ite information must be stored because the sram cannot perform the last word write to the array without conflicting with t he read. the data stays in this register until the next write cycle occurs. on the first write cycle after the read(s), the stored data from the earlier write is written into the sram array. this is called a posted write. if a read is performed on the sa me address on which a write is performed in the previous cycle, the sram reads out the most current data. the sram does this by bypassing the memory array and reading the data from the registers. depth expansion depth expansion requires replicating the ld control signal for each bank. all other control signals can be common between banks as appropriate. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee im pedance matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq =1.5v. the output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. echo clocks echo clocks are provided on the ddr -ii+ to simplify data capture on high-speed systems. two echo clocks are generated by the ddr-ii+. cq is referenced with respect to k and cq is refer- enced with respect to k . these are free-running clocks and are synchronized to the input clock of the ddr-ii+. the timings for the echo clocks are shown in the ?switching characteristics? on page 22 . valid data indicator (qvld) qvld is provided on the ddr-ii+ to simplify data capture on high speed systems. the qvld is g enerated by the ddr-ii+ device along with data output. this signal is also edge-aligned with the [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 9 of 27 echo clock and follows the timing of any data pin. this signal is asserted half a cycle befo re valid data arrives. dll these chips utilize a delay lock loop (dll) that is designed to function between 120 mhz and the specified maximum clock frequency. the dll may be disabled by applying ground to the doff pin. when the dll is turned off, the device behaves in ddr-i mode (with 1.0 cycle latency and a longer access time). for more information, refer to the application note, ?dll consid- erations in qdrii/ddrii/qdrii +/ddrii+?. the dll can also be reset by slowing or stopping the input clocks k and k for a minimum of 30 ns. however, it is not necessary for the dll to be reset in order to lock to the desired frequency. during power up, when the doff is tied high, the dll gets locked after 2048 cycles of stable clock. application example figure 1 shows two ddr-ii+ used in an application. figure 1. application example truth table the truth table for the cy7c1146v18, cy7c11 57v18, cy7c1148v18, and cy7c1150v18 follows. [3, 4, 5, 6, 7, 8] operation k ld r/w dq dq write cycle: load address; wait o ne cycle; input write data on consecutive k and k rising edges. l ? h l l d(a) at k (t + 1) d(a + 1) at k (t + 1) read cycle: (2.0 cycle latency) load address; wait tw o cycle; read data on consecutive k and k rising edges. l ? h l h q(a) at k (t + 2) q(a + 1) at k (t + 2) nop: no operation l ? h h x high-z high-z standby: clock stopped stopped x x previous state previous state bus master (cpu or asic) dq addresses cycle start r/w source clk source clk echo clock1/echo clock1 echo clock2/echo clock2 r = 250ohms ld r/w dq a sram#1 k zq cq/cq k r = 250ohms ld r/w dq a sram#2 k zq cq/cq k notes 2. the above applicati on shows two ddr-ii+ used. 3. x = ?don?t care,? h = logic high, l = logic low, represents rising edge. 4. device powers up deselected and the outputs in a tri-state condition. 5. ?a? represents address location latched by the devices when transaction was initiated and a + 1 represents the addresses sequ ence in the burst. 6. ?t? represents the cycle at which a read/write operation is star ted. t + 1 and t + 2 are the first and second clock cycles su cceeding the ?t? clock cycle. 7. data inputs are registered at k and k rising edges. data outputs are delivered on k and k rising edges. 8. it is recommended that k = k = high when clock is stopped. this is not essential, but permits most rapid restart by overcoming transmission line charging s ymmetrically. [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 10 of 27 write cycle descriptions the write cycle descriptions of cy7c 1146v18 and cy7c11 48v18 follows. [3, 9] bws 0 / nws 0 bws 1 / nws 1 k k comments l l l ? h ? when the data portion of a write sequence is active : cy7c1146v18 ? both nibbles (d [7:0] ) are written into the device, cy7c1148v18 ? both bytes (d [17:0] ) are written into the device. l l ? l ? h when the data portion of a write sequence is active : cy7c1146v18 ? both nibbles (d [7:0] ) are written into the device, cy7c1148v18 ? both bytes (d [17:0] ) are written into the device. l h l ? h ? when the data portion of a write sequence is active : cy7c1146v18 ? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. cy7c1148v18 ? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. l h ? l ? h when the data portion of a write sequence is active : cy7c1146v18 ? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. cy7c1148v18 ? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. h l l ? h ? when the data portion of a write sequence is active: cy7c1146v18 ? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. cy7c1148v18 ? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h l ? l ? h when the data portion of a write sequence is active : cy7c1146v18 ? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. cy7c1148v18 ? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h h l ? h ? no data is written into the devices when this portion of a write operation is active. h h ? l ? h no data is written into the devices when this portion of a write operation is active. the write cycle descriptions of cy7c1146v18 follows. [3, 9] bws 0 kk comments l l ? h ? when the data portion of a write sequence is active , the single byte (d [8:0] ) is written into the device. l ? l ? h when the data portion of a write sequence is active , the single byte (d [8:0] ) is written into the device. h l ? h ? no data is written into the device when this portion of a writ e operation is active. h ? l ? h no data is written into the device when this portion of a writ e operation is active. note 9. is based on a write cycle was initiated in accordance with the write cycle description truth table. alter bws 0 , bws 1 , bws 2 , and bws 3 on different portions of a write cycle, as long as the setup and hold requirements are achieved. [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 11 of 27 the write cycle descriptions of cy7c1148v18 follows, [3, 9] bws 0 bws 1 bws 2 bws 3 kk comments lllll ? h?when the data portion of a write sequence is active, all four bytes (d [35:0] ) are written into the device. llll?l ? hwhen the data portion of a write sequence is active, all four bytes (d [35:0] ) are written into the device. l h h h l ? h ? when the data portion of a write sequence is active, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. l h h h ? l ? h when the data portion of a write sequence is active, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. h l h h l ? h ? when the data portion of a write sequence is active, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h l h h ? l ? h when the data portion of a write sequence is active, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h h l h l ? h ? when the data portion of a writ e sequence is active, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h l h ? l ? h when the data portion of a write sequence is active, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h h l l ? h ? when the data portion of a writ e sequence is active, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h l ? l ? h when the data portion of a writ e sequence is active, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. hhhhl ? h?no data is written into the device when this portion of a write operation is active. hhhh?l ? hno data is written into the device when this portion of a write operation is active. [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 12 of 27 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. th is part is fully compliant with ieee standard 1149.1-2001. t he tap operates using jedec standard 1.8v io logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power up, t he device comes up in a reset state which does not interfere wit h the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially in put information in to the registers and connect to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for more information on loading the instruction register, see the ?tap controller state diagram? on page 14 . tdi is internally pulled up and unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data out from the registers. the output is active depending upon the current state of the tap state machine (see instruction codes). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. select only one register at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register serially load three-bit instructions into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in ?tap controller block diagram? on page 15 . upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. use the extest, sample/preload, a nd sample z instructions to capture the contents of t he input and output ring. the ?boundary scan order? on page 18 show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the ?identification register definitions? on page 17 . tap instruction set eight different instructions are possible with the three-bit instruction register. all combinatio ns are listed in the instruction code table. three of these inst ructions are listed as reserved and must not be used. the other fi ve instructions are described in detail in the following section. instructions are loaded into the t ap controller during the shift-ir state when the instruction register is placed between tdi and tdo. when this state is active, instructions are shifted through the instruction register th rough the tdi and tdo pins. to execute the instruction after it is shifted in, the tap controller needs to be moved into the update-ir state. [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 13 of 27 idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and enables the idcode to be shifted out of the device when the tap controller enters the shift-dr st ate. the idcode instruction is loaded into the instruction register upon power up or whenever the tap controller is supplied a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr st ate. the sample z command puts the output bus into a high-z state until the next command is supplied when the update ir state is active. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruc- tion register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that when the capture-dr state is ac tive, an input or output under- goes a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. re- peatable results may not be possible. to guarantee that the boundary sc an register captures the cor- rect value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock a sample/preload instruct ion. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells be- fore the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when require d ? that is, wh ile data captured is shifted out, shift in the preloaded data. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system ou tput pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit 47. when this scan cell, called the ?extest output bus tri-state?, is latched into the preload register the update-dr state in the tap controller, it directly controls th e state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bit places the outpu t bus into a high-z condition. set this bit by entering the sample/preload or extest command, and then shifting the desired bit into that cell, when the shift-dr state is active. when the update-dr is active, the value loaded into that shift-register cell latches into the preload register. when the extest instructi on is entered, this bit directly controls the output q-bus pins. note that this bit is preset high to enable the output when the device is powered up, and also when the tap controller is in the test-logic-reset state. reserved these instructions are not impl emented but are reserved for future use. do not use these instructions. [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 14 of 27 tap controller state diagram figure 2 shows the tap controller state diagram. [10] figure 2. tap controller state diagram test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 note 10. the 0/1 next to each state represents the value at tms at the rising edge of tck. [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 15 of 27 tap controller block diagram figure 3. tap controller block diagram tap electrical characteristics the tap electrical characteristics ta ble over the operating range follows. [11, 12, 13] parameter description test conditions min max unit v oh1 output high voltage i oh = ? 2.0 ma 1.4 v v oh2 output high voltage i oh = ? 100 a1.6 v v ol1 output low voltage i ol = 2.0 ma 0.4 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 0.65 v dd v dd + 0.3 v v il input low voltage ?0.3 0.35 v dd v i x input and output load current gnd v i v dd ? 55 a 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms notes 11. these characteristics pertain to the tap inputs (tms, tck, td i, and tdo). parallel load levels are specified in the electric al characteristics table. 12. overshoot: v ih (ac) < v ddq + 0.35v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 0.3v (pulse width less than t cyc /2). 13. all voltage referenced to ground. [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 16 of 27 tap ac switching characteristics the tap ac switching characteristics table over the operating range follows. [14, 15] parameter description min max unit t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high 20 ns t tl tck clock low 20 ns setup times t tmss tms setup to tck clock rise 5 ns t tdis tdi setup to tck clock rise 5 ns t cs capture setup to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns tap timing and test condition the tap timing and test conditions for the cy7c1146v18, cy7c1157v18, cy7c1148v18, and cy7c1150v18 follows. [15] figure 4. tap timing and test conditions t tl t th (a) tdo c l = 20 pf z 0 = 50 ? gnd 0.9v 50 ? 1.8v 0v all input pulses 0.9v test clock test mode select tck tms test data in tdi test data out t tcyc t tmsh t tmss t tdis t tdih t tdov t tdox tdo notes 14. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 15. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 17 of 27 identification regi ster definitions instruction field value description cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 revision number (31:29) 000 000 000 000 version number. cypress device id (28:12) 110101111 00000101 11010111100001101 11010111100010101 11010111100100101 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 1 1 indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 instruction codes instruction code description extest 000 captures the input output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the input output ring co ntents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 18 of 27 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 27 11h 54 7b 81 3g 1 6p 28 10g 55 6b 82 2g 26n 299g 566a 831j 3 7p 30 11f 57 5b 84 2j 4 7n 31 11g 58 5a 85 3k 57r 329f 594a 863j 6 8r 33 10f 60 5c 87 2k 7 8p 34 11e 61 4b 88 1k 8 9r 35 10e 62 3a 89 2l 9 11p 36 10d 63 1h 90 3l 10 10p 37 9e 64 1a 91 1m 11 10n 38 10c 65 2b 92 1l 12 9p 39 11d 66 3b 93 3n 13 10m 40 9c 67 1c 94 3m 14 11n 41 9d 68 1b 95 1n 15 9m 42 11b 69 3d 96 2m 16 9n 43 11c 70 3c 97 3p 1711l 449b 711d 982n 18 11m 45 10b 72 2c 99 2p 19 9l 46 11a 73 3e 100 1p 20 10l 47 internal 74 2d 101 3r 21 11k 48 9a 75 2e 102 4r 22 10k 49 8b 76 1e 103 4p 23 9j 50 7c 77 2f 104 5p 24 9k 51 6c 78 3f 105 5n 25 10j 52 8a 79 1g 106 5r 26 11j 53 7a 80 1f [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 19 of 27 power up sequence in ddr-ii+ sram during power up, when the doff is tied high, the dll gets locked after 2048 cycles of stable clock. ddr-ii+ srams must be powered up and initialized in a predefined manner to prevent undefined operations. power up sequence apply power with doff tied high (all other inputs can be high or low) ? apply v dd before v ddq ? apply v ddq before v ref or at the same time as v ref provide stable power and clock (k, k ) for 2048 cycles to lock the dll. dll constraints dll uses k clock as its synchronizing input. the input must have low phase jitter, which is specified as t kc var . the dll functions at frequencies down to 120 mhz. if the input clock is unstable and the dll is enabled, then the dll may lock onto an incorrect frequency, causing unstable sram behavior. to av oid this, provid e 2048 cycles stable clock to relock to the desired clock frequency. power up waveforms figure 5. power up waveforms k k fix high (tie to v ddq ) v dd /v ddq doff clock start (clock starts after v dd /v ddq is stable) unstable clock > 2048 stable clock start normal operation ~ ~ ~ ~ v dd /v ddq stable (< + 0.1v dc per 50 ns) [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 20 of 27 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ................................ ?65c to + 150c ambient temperature with powe r applied ?55c to + 125c supply voltage on v dd relative to gnd .......?0.5v to + 2.9v supply voltage on v ddq relative to gnd..... ?0.5v to + v dd dc applied to outputs in high-z .........?0.5v to v ddq + 0.3v dc input voltage [12] ............................... ?0.5v to v dd + 0.3v current into outputs (low)......................................... 20 ma static discharge voltage (mil-std-883, m 3015).... >2001v latch up current........ .............. .............. .............. ... >200 ma operating range range ambient temperature v dd [16] v ddq [16] commercial 0c to +70c 1.8 0.1v 1.4v to v dd industrial ?40c to +85c electrical characteristics the dc electrical characteristics over the operating range follows. [13] parameter description test conditions min typ max unit v dd power supply voltage 1.7 1.8 1.9 v v ddq io supply voltage 1.4 1.5 v dd v v oh output high voltage note 17 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v ol output low voltage note 18 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ?0.1 ma, nominal impedance v ddq ? 0.2 v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss 0.2 v v ih input high voltage v ref + 0.1 v ddq + 0.15 v v il input low voltage ?0.15 v ref ? 0.1 v i x input leakage current gnd v i v ddq ?2 2 a i oz output leakage current gnd v i v ddq, output disabled ?2 2 a v ref input reference voltage [19] typical value = 0.75v 0.68 0.75 0.95 v i dd v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 300 mhz 850 ma 333 mhz 920 ma 375 mhz 1020 ma i sb1 automatic power down current max v dd , both ports deselected, v in v ih or v in v il f = f max = 1/t cyc , inputs static 300 mhz 250 ma 333 mhz 260 ma 375 mhz 290 ma ac input requirements over the operating range [12] parameter description test conditions min typ max unit v ih input high voltage v ref + 0.2 ? v ddq + 0.24 v v il input low voltage ?0.24 ? v ref ? 0.2 v notes 16. power up: is based on a linear ramp from 0v to v dd (min) within 200 ms. during this time v ih < v dd and v ddq < v dd . 17. outputs are impedance controlled. i oh = ?(v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 18. outputs are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 19. v ref (min) = 0.68v or 0.46 v ddq , whichever is larger, v ref (max) = 0.95v or 0.54 v ddq , whichever is smaller. [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 21 of 27 capacitance tested initially and after any design or process change that may affect these parameters . parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 1.8v v ddq = 1.5v 5pf c clk clock input capacitance 6 pf c o output capacitance 7pf thermal resistance tested initially and after any design or process change that may affect these parameters . parameter description test conditions 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 17.2 c/w jc thermal resistance (junction to case) 4.15 c/w ac test loads and waveforms figure 6. ac test loads and waveforms 1.25v 0.25v r = 50 ? 5pf including jig and scope all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75v v ref = 0.75v [20] 0.75v under test 0.75v device under test output 0.75v v ref v ref output zq zq (a) slew rate= 2 v/ns rq = 250 ? (b) rq = 250 ? note 20. unless otherwise noted, test conditions are based upon a signal transition time of 2v/ns, timing reference levels of 0.75v, v ref = 0.75v, rq = 250 ? , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads. [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 22 of 27 switching characteristics over the operating range [20, 21] cypress parameter consortium parameter description 375 mhz 333 mhz 300 mhz unit min max min max min max t power v dd (typical) to the first access [22] 1?1?1?ms t cyc t khkh k clock cycle time 2.66 8.40 3.0 8.40 3.3 8.40 ns t kh t khkl input clock (k/k ) high 0.425?0.425?0.425? t cyc t kl t klkh input clock (k/k ) low 0.425?0.425?0.425? t cyc t khk h t khk h k clock rise to k clock rise (rising edge to rising edge) 1.13 ? 1.28 ? 1.40 ? ns setup times t sa t avkh address setup to k clock rise 0.4 ? 0.4 ? 0.4 ? ns t sc t ivkh control setup to k clock rise (ld , r/w ) 0.4 ? 0.4 ? 0.4 ? ns t scddr t ivkh double data rate control setup to clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.28 ? 0.28 ? 0.28 ? ns t sd t dvkh d [x:0] setup to clock (k/k ) rise 0.28?0.28?0.28? ns hold times t ha t khax address hold after k clock rise 0.4 ? 0.4 ? 0.4 ? ns t hc t khix control hold after k clock rise (ld , r/w ) 0.4 ? 0.4 ? 0.4 ? ns t hcddr t khix double data rate control hold after clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.28 ? 0.28 ? 0.28 ? ns t hd t khdx d [x:0] hold after clock (k/k ) rise 0.28?0.28?0.28? ns output times t co t chqv k/k clock rise to data valid ? 0.45 ? 0.45 ? 0.45 ns t doh t chqx data output hold after k/k clock rise (active to active) ?0.45 ? ?0.45 ? ?0.45 ? ns t ccqo t chcqv k/k clock rise to echo clock valid ? 0.45 ? 0.45 ? 0.45 ns t cqoh t chcqx echo clock hold after k/k clock rise ?0.45 ? ?0.45 ? ?0.45 ? ns t cqd t cqhqv echo clock high to data valid ? 0.2 ? 0.2 ? 0.2 ns t cqdoh t cqhqx echo clock high to data invalid ?0.2 ? ?0.2 ? ?0.2 ? ns t cqh t cqhcql output clock (cq/cq ) high [23] 0.88 ? 1.03 ? 1.15 ? ns t cqhcq h t cqhcq h cq clock rise to cq clock rise [23] (rising edge to rising edge) 0.88 ? 1.03 ? 1.15 ? ns t chz t chqz clock (k/k ) rise to high-z (active to high-z) [24, 25] ? 0.45 ? 0.45 ? 0.45 ns t clz t chqx1 clock (k/k ) rise to low-z [24, 25] ?0.45 ? ?0.45 ? ?0.45 ? ns t qvld t qvld echo clock high to qvld valid [26] ?0.20 0.20 ?0.20 0.20 ?0.20 0.20 ns dll timing t kc var t kc var clock phase jitter ? 0.20 ? 0.20 ? 0.20 ns t kc lock t kc lock dll lock time (k) 2048 ? 2048 ? 2048 ? cycles t kc reset t kc reset k static to dll reset [27] 30?30?30? ns notes 21. when a part with a maximum frequency above 300 mhz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 22. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd minimum initially before a read or write operation can be initiated. 23. these parameters are extrapolated from the input timing parameters (t khk h ? 250 ps, where 250 ps is the internal jitter. an input jitter of 200 ps (t kc var ) is already included in the t khk h ). these parameters are only guaranteed by design and are not tested in production. 24. t chz , t clz , are specified with a load capacitance of 5 pf as in (b) of ac test loads. transition is measured 100 mv from steady-state voltage. 25. at any voltage and temperature t chz is less than t clz and t chz less than t co . 26. t qvld spec is applicable for both risi ng and falling edges of qvld signal. 27. hold to >v ih or cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 23 of 27 switching waveforms read/write/deselect sequence figure 7. waveform for 2.0 cycle read latency [28, 29, 30] dont care undefined 1 2 3 4 5 6 7 8 9 10 read read read nop write write t nop 11 k k ld r/w a t kh t kl t cyc t hc t sa t ha sc a0 a1 a2 a3 a4 cq cq qvld qvld t nop t qvld t t ccqo t cqoh t t cqoh qvld t nop dq khkh 12 (read latency = 2.0 cycles) nop nop ccqo t sd hd t sd t hd t clz t chz d20 d21 d30 d31 t cqdoh q00 q11 q01 q10 t doh t co q40 q41 t cqd t t t cqh cqhcqh notes 28. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, i.e., a0 + 1. 29. outputs are disabled (high-z) one clock cycle after a nop. 30. the third nop cycle between read to write transition is not necessary for correct device opera tion when read latency = 2.0 c ycles; however at high frequency operation, it may be required to avoid bus contention. [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 24 of 27 ordering information not all of the speed, package and temperature ranges are available. contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range 375 cy7c1146v18-375bzc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial cy7c1157v18-375bzc cy7c1148v18-375bzc cy7c1150v18-375bzc cy7c1146v18-375bzxc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1157v18-375bzxc cy7c1148v18-375bzxc cy7c1150v18-375bzxc cy7c1146v18-375bzi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1157v18-375bzi cy7c1148v18-375bzi cy7c1150v18-375bzi cy7c1146v18-375bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1157v18-375bzxi cy7c1148v18-375bzxi cy7c1150v18-375bzxi 333 cy7c1146v18-333bzc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial cy7c1157v18-333bzc cy7c1148v18-333bzc cy7c1150v18-333bzc cy7c1146v18-333bzxc 51-85180 165-vall fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1157v18-333bzxc cy7c1148v18-333bzxc cy7c1150v18-333bzxc CY7C1146V18-333BZI 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1157v18-333bzi cy7c1148v18-333bzi cy7c1150v18-333bzi cy7c1146v18-333bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1157v18-333bzxi cy7c1148v18-333bzxi cy7c1150v18-333bzxi [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 25 of 27 300 cy7c1146v18-300bzc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial cy7c1157v18-300bzc cy7c1148v18-300bzc cy7c1150v18-300bzc cy7c1146v18-300bzxc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1157v18-300bzxc cy7c1148v18-300bzxc cy7c1150v18-300bzxc cy7c1146v18-300bzi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1157v18-300bzi cy7c1148v18-300bzi cy7c1150v18-300bzi cy7c1146v18-300bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1157v18-300bzxi cy7c1148v18-300bzxi cy7c1150v18-300bzxi ordering information (continued) not all of the speed, package and temperature ranges are available. contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range [+] feedback [+] feedback
cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 document number: 001-06621 rev. *c page 26 of 27 package diagram figure 8. 165-ball fbga (13 x 15 x 1.4 mm), 51-85180 a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.350.06 seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 - 0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / design 4.6c package code : bb0ac 51-85180-*a [+] feedback [+] feedback
document number: 001-06621 rev. *c revised june 21, 2007 page 27 of 27 qdr? is a trademark of cypress semiconductor corp. qdr rams and qu ad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all product and company names mentioned in this document are the trademarks of their respective holders. cy7c1146v18 cy7c1157v18 cy7c1148v18 cy7c1150v18 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy7c1146v18/cy7c1157v18/cy7c1148v18 /cy7c1150v18, 18-mbit ddr- ii+ sram 2-word burst architecture (2.0 cycle read latency) document number: 001-06621 rev. ecn no. issue date orig. of change description of change ** 430351 see ecn nxr new data sheet *a 461654 see ecn nxr revised the mpns from cy7c1157bv18 to cy7c1146v18 cy7c1148bv18 to cy7c1157v18 cy7c1150bv18 to cy7c1148v18 changed t th and t tl from 40 ns to 20 ns, changed t tmss , t tdis , t cs , t tmsh , t tdih , t ch from 10 ns to 5 ns and changed t tdov from 20 ns to 10 ns in tap ac switching characteristics table modified power up waveform *b 497629 see ecn nxr changed the v ddq operating voltage to 1.4v to v dd in the features section, in operating range table and in the dc electrical characteristics table added foot note in page 1 changed the maximum rating of ambient temperature with power applied from ?10c to +85c to ?55c to +125c changed v ref (max) spec from 0.85v to 0.95v in the dc electrical character- istics table and in the note below the table updated note 21 to specify overshoot and undershoot spec updated ja and jc values removed x9 part and its related information updated foot note 24 *c 1175245 see ecn vkn/kkvtmp converted from preliminary to final added x8 and x9 parts updated logic block diagram for x18 and x36 parts changed i dd values from 794 ma to 1020 ma for 375 mhz, 733 ma to 920 ma for 333 mhz, 685 ma to 850 ma for 300 mhz changed i sb values from 227 ma to 290 ma for 375 mhz, 212 ma to 260 ma for 333 mhz, 201 ma to 250 ma for 300 mhz changed t cyc(max) spec to 8.4 ns for all speed bins changed ja value from 13.48 c/w to 17.2 c/w updated ordering information table [+] feedback [+] feedback

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